Typically, thin film transistor or active-matrix pixel circuits require careful alignment of the source-drain layer(s) to the gate layer. However, aligning layers in printed (organic) electronic circuits is a challenge, particularly on flexible substrates where substrate distortion and shrinkage often occur. It is difficult to compensate for such deformation of the substrate. This has significance because misalignment can lead to a non-working transistor.
To attempt to solve the problem, wide gate features have been used to ensure the source-drain region overlaps with the gate region. This approach and resulting overlap, however, cause high and undesired parasitic capacitances.
To illustrate these problems, FIGS. 1(a)-(e) show the elements of a printed pixel array. Such an array is typically used in active-matrix backplanes for displays, image sensors or other sensor arrays. As shown, a gate layer 10 (FIG. 1(a)), having defined gate features, and a data layer 12 (FIG. 1(b)), with data lines and pixel pads, should be aligned so that the gate features end up underneath the channel region 14 to form a thin film transistor (TFT) 16 (FIG. 1(c)). As noted above, misalignment can lead to non-functioning TFTs (FIG. 1(d)). In this regard, the source s and gate g overlap; however, there is no overlap between the gate g and the drain d. Thus, the TFT will not function properly. If the gate feature is chosen to be wide to compensate for potential misalignment as alluded to above, then the excessive parasitic capacitance due to overlapping s/g or s/d regions can cause problems (e.g. feedthrough voltage in pixels or reduced switching speed of TFTs) (FIG. 1(e)). So, solutions to these problems are desired.
Self-aligned patterning methods—using, for example, backside exposure of photoresist—are used in photolithographic patterning methods. However, for electronic circuits patterned using printing methods, better solutions are desired.